The need to reduce transistor size is a perennial problem to be solved in the art of integrated circuits. One way that the Background Art reduced transistor size was to reduce the length of the channel. Doing so effectively reduced the overall footprint of the transistor. But then a minimum channel length (relative to other physical parameters of the transistor) was achieved below which problems were created, e.g., short channel effects.
The Background Art responded by developing a transistor architecture that reduced the transistor's footprint size while maintaining at least the minimum channel length. The solution can be explained via analogy to an inchworm. FIGS. 5A-5B are side views that depict stages of the peculiar form of locomotion used by an inchworm 602. In FIG. 5A, a head 604 and a tail 606 of inchworm 602 are close together while a middle section 608 thereof is hunched upward (or, in other words, folded almost in half). In FIG. 5B, inchworm 602 has moved its head 604 forward while keeping its tail 606 in the same position as in FIG. 5A, which causes middle section 608 to be stretched horizontally relative to FIG. 5A. In FIG. 5C, inchworm 602 has kept its head 604 in the same position as in FIG. 5B, but has moved its tail 606 to again be located near its head 604. As such, inchworm 602 has adopted in FIG. 5C the same posture as in FIG. 5A.
The larger footprint transistor architecture according to the Background Art is analogous to the posture of inchworm 602 in FIG. 5B, where the channel corresponds to the horizontally stretched middle section 608 of inchworm 602. The smaller footprint transistor architecture according to the Background Art is analogous to the posture of inchworm 602 in FIGS. 5A and 5C, where the channel corresponds to the hunched-upward or folded middle section 608.
FIG. 6 is a three-quarter perspective view of the smaller footprint architecture according to the Background Art, which is generally referred to as a FinFET and particularly here as a triple gate FinFET 700, i.e., FET having a channel in the shape of a fin 702b (obscured in FIG. 6 but see FIG. 7) formed on a buried oxide (BOX) structure 701 between a source region 702a and a drain region 702C. Gate electrode 706 conforms (as does interposed gate oxide layer 704) to the shape of channel 704
FIG. 7 is a cross-sectional view of Background Art FinFET 700 taken along line VII-VII′ of FIG. 6. Recall that the inversion layer induced in a channel is located next to gate oxide 704 and tends to be rather shallow. An idealized effect of the fin-shaped channel 704 gate electrode 706 is as if three separate inversion layers are induced, namely a first inversion layer 708a, a second inversion layer 708b and a third inversion layer 708C. Hence, FinFET 700 is referred to as a triple-gate FinFET.
FIGS. 8A-8B are cross-sectional views of two stages in the manufacture of a multi-gate FinFET according to the Background Art. More particularly, FIGS. 8A-8B depict stages in the formation of the fin of the FinFET. In FIG. 8A, a silicon layer 220 is formed on a buried oxide (BOX) structure 210, which is formed on a silicon substrate 220. A silicon plug 810 is formed to fill an opening in oxide layer 510. Plug 810 is grown by selective epitaxial growth (SEG). In FIG. 8B, the portion of plug 810 extending above oxide 510 has been removed by CMP.
Returning to FIG. 7, as a practical matter, the electrostatic field induced by a voltage on gate electrode, e.g., 706, is not uniform along gate electrode 706. Rather, the electrostatic field tends to be concentrated in the corners, as indicated by the shaded regions 710a and 710b in FIG. 7. Consequently, inversion layers form in the corners before forming all along gate electrode 706. This lowers a threshold voltage for the corners relative to the sides, leading to higher current flow at the corners and generally non-uniform performance of the FinFET.
The Background Art recognized that such a corner phenomenon could be mitigated if the corners could be rounded. Accordingly, efforts have been made to remove material from the substantially square corners, e.g., by dry etching, in order to achieve an approximation of rounded corners. Despite many attempts, the Background Art has not been able to develop a technique to remove material from square corners of triple-gate FinFET 700 (or a double-gate version thereof that does not irreparably damage the remaining portion of fin 702b or result in a non-uniform width thereof.